This invention relates generally to logic circuitry and, more particularly, to an ECL logic gate employing a multifunction current mirror circuit.
A known ECL logic gate includes a current sourced emitter follower output and a current mirror circuit to develop the logic gate's switching current. In this case, three separate current paths are utilized, one of which comprises of a resistor and a diode coupled NPN transistor coupled in series between V.sub.CC (typically ground) and V.sub.EE (typically -5.2 volts). Thus, current always flows in this current path increasing the gates power consumption. While this may not be of great concern on a per gate basis, the unwanted power consumption becomes significant when the gate is used on gate arrays which may include over 10,000 gates. Furthermore, if the per gate component count can be reduced, there is a significant savings in die area on the entire array.